1. Field of the Invention
The present invention relates to the field of digital-to-analog converters (DACs)
2. Prior Art
Designing multiple-channel (such as greater than 8), high-resolution DACs (such as greater than 14-bits) in minimum die area has always been a challenging problem in the analog world. In many level-setting and closed loop applications, multiple high-resolution DAC channels are required that need guaranteed monotonic behavior and better than 12-bits of absolute accuracy.
Normally, R-2R DACs are used for high resolution and accuracy. The resolution of an untrimmed R-2R DAC is limited to 10 to 12-bits. In order to guarantee differential nonlinearity (DNL) at greater than a 14-bit level, a significant amount of trimming is involved, which in turn adds substantial cost to the integrated circuit. Also since the input resistance looking into the DACs is relatively smaller for multi channel DACs, precision buffers are needed for the high and low references for such architecture. Precision buffers are expensive in terms of die area.
Integrating multiple channels of independent high-resolution DACs also contributes to significant die-area that adds both to the cost and the footprint of the integrated circuit. Sample and hold approaches have been proposed that cut down the die-area for a multi-channel, high resolution DAC, but this generally results in pedestal, droop and feedthrough errors owing to the sampling nature of the system.